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HT83FXX Flash Type Voice OTP MCU
Technical Document
* Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: 2.7V~3.6V * System clock: 4MHz~8MHz * Crystal and RC system oscillator * 12 I/O pins * I2C/SPI Bus Serial Interface, shared with PB * 2K15 OTP Program Memory * Between 2M8 bit and 128K8 bit flash type data * 4-level subroutine nesting * 2.7V Low voltage detection, tolerance 5% * Integrated LDO regulator in
HT83F10P/20P/40P/60P/80P
* Power-down function and wake-up feature reduce
power consumption
* Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz)
memory
* 808 Data Memory * Two 8-bit programmable timer counter with 8-stage
system clock at VDD= 3.6V
* 63 powerful instructions * One reset pin * Flash Data Memory can be re-programmed up to
prescaler and one time base counter
* 12-bit high quality voltage type D/A output * PWM circuit direct drive speaker * Watchdog Timer function
100,000 times
* Flash Data Memory data retention > 10 years * 44-pin QFP package
General Description
The flash type voice series of MCUs have OTP type Program Memory and Flash type Voice Memory. The devices are 8-bit high performance microcontrollers which include a voice synthesizer and tone generator. They are designed for applications which require multiple I/Os and sound effects, such as voice and melody. The devices can provide various sampling rates and beats, tone levels, tempos for speech synthesizer and melody generator. They also include two integrated high quality, voltage type DAC outputs and voltage type PWM outputs. The devices are excellent solutions for versatile voice and sound effect product applications with their efficient MCU instructions providing the user with programming capability for powerful custom applications. The system frequency can be up to 8MHz at an operating voltage of 2.7V and include a power-down function to reduce power consumption. The MCU flash voice memory capacity ranges from 2M8 bit to 128K8 bit, into which the user can download their voice data repeatedly.
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Selection Table
The devices include a comprehensive range of features, with most features common to all devices. The main features distinguishing them are Flash Voice Memory capacity. The functional differences between the devices are shown in the following table.
OTP Program Memory 2K15 Flash Voice Memory 128K8 I2C/ SPI O
Part No. HT83F10 HT83F10P HT83F20 HT83F20P HT83F40 HT83F40P HT83F60 HT83F60P HT83F80 HT83F80P
VDD 2.7V~3.6V 3.3V 2.7V~3.6V 3.3V 2.7V~3.6V 3.3V 2.7V~3.6V 3.3V 2.7V~3.6V 3.3V
VIN 3/4 3.6V~24V 3/4 3.6V~24V 3/4 3.6V~24V 3/4 3.6V~24V 3/4 3.6V~24V
Data Memory
Voice Capacity
I/O
8-bit Timer
D/A
Package Types
808
32sec
12
2
12-bit, PWM 12-bit, PWM 12-bit, PWM 12-bit, PWM 12-bit, PWM
44QFP
2K15
808
256K8
64sec
12
2
O
44QFP
2K15
808
512K8
128sec
12
2
O
44QFP
2K15
808
1024K8
256sec
12
2
O
44QFP
2K15
808
2048K8
512sec
12
2
O
44QFP
Note: For devices that exist in more than one package formats, the table reflects the situation for the larger package. Voice length is estimated by 32K-bit data rate, or 8K sampling rate and 4 bit ADPCM compress mode.
Block Diagram
W a tc h d o g T im e r 8 - b it R IS C MCU C o re Low V o lta g e D e te c tio n PW M SPI F u n c tio n I2C F u n c tio n W a tc h d o g T im e r O s c illa to r R eset C ir c u it In te rru p t C o n tr o lle r R C /C ry s ta l O s c illa to r
H T 8 3 F 1 0 P /2 0 P /4 0 P /6 0 P /8 0 P LDO S ta c k
OTP ROM P ro g ra m M e m o ry
F la s h D a ta M e m o ry
R A M D a ta M e m o ry
I/O
P o rts
8 - b it T im e r
D /A C o n v e rte rs
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Pin Assignment
HOL N C N S N N W VSS N SC O O C C C C C C D P K S P K S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 F F 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 C C C C D HOL N C N S N N W VSS N SC
P P P P P P P P P P
SI A7 A6 A5 A4 A3 A2 A1 A0 B0 B1
33 32 31 30 29 28 27 26 25 24 23
H T 8 3 F 1 0 /2 0 /4 0 /6 0 /8 0 4 4 Q F P -A
VDD NC NC VSS PW M PW M VDD VDD AUD VSS OSC P A
F P P P 2 P 1 P P A P P P 2 P P
SI A7 A6 A5 A4 A3 A2 A1 A0 B0 B1
33 32 31 30 29 28 27 26 25 24 23
H T 8 3 F 1 0 P /2 0 P /4 0 P /6 0 P /8 0 P 4 4 Q F P -A
VDDF LD O _O U T L D O _ IN VSSP PW M2 PW M1 VDDP VDDA AUD VSSA OSC2
Pin Description
Pin Name I/O Options Wake-up, Pull-high or None Description Bidirectional 8-bit I/O port, Each bit can be configured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on this port have pull-high resistors. Bidirectional 4-bit I/O port. Each bit can be configured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on this port have pull-high resistors. Pins PB0~PB3 are pin-shared with SPI flash control and I2C control pins SDO/SDA, SCK/SCL, SDI and SCS. Data output pin Clock output pin. Data input pin. Select signal. Audio output for driving external transistor or power amplifier. PWM circuit direct speaker drive Schmitt trigger reset input. Active low OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. Positive digital power supply Negative digital power supply, ground PWM negative power supply, ground PWM positive power supply Negative DAC circuit power supply, ground Positive DAC circuit Power supply
OSC1 RES V D D _ P B IO VDD VSS SCS DI CLK DO PB3 PB2
OSC1 RES V D D _ P B IO VDD VSS SCS DI CLK DO PB3 PB2
PA0~PA7
I/O
PB0/SDO/SDA PB1/SCK/SCL PB2/SDI PB3/SCS DO CLK DI SCS AUD PWM1, PWM2 RES OSC1 OSC2 VDD VSS VSSP VDDP VSSA VDDA
I/O
Pull-high or None
O O I O O O I
3/4 3/4 3/4 3/4 CMOS 3/4 3/4 Crystal or RC 3/4 3/4 3/4 3/4 3/4 3/4
3/4
3/4 3/4 3/4 3/4 3/4 3/4
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Pin Name VDD_PBIO LDO_OUT LDO_IN CS SI SO SCK HOLD WP VDDF VSSF I/O 3/4 O I I I O I I I 3/4 3/4 Options 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Description PB I/O external positive power supply (determine by option) LDO output LDO input Flash data memory chip select pin Flash data memory data input pin Flash data memory data output pin Flash data memory clock input pin Hold, pause the device without deselecting Flash data memory Flash data memory write protect pin Positive Flash data memory Power supply Negative Flash data memory Power supply, ground
Note: Each pin on PA can be programmed through a configuration option to have a wake-up function. Individual pins can be selected to have pull-high resistors.
Absolute Maximum Ratings
Supply Voltage ...........................VSS+2.7V to VSS+3.6V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ..........................-50C to +125C Operating Temperature.........................-40C to +85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Test Conditions Symbol VDD fSYS Parameter VDD Operating Voltage System Frequency 3/4 3V Conditions fSYS=4MHz/8MHz ROSC=275kW ROSC=144kW IDD ISTB1 ISTB2 VIL1 VIH1 VIL2 VIH2 VLVD VLDO VLDO_IN Operating Current Standby Current (WDT Off) Standby Current (WDT On) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Detection LDO Output Voltage LDO Input Voltage 3V 3V 3V 3V 3V 3V 3V 3/4 3/4 3/4 LVD 2.7V VLDO_IN>3.6V 3/4 No load, fSYS=4MHz No load, fSYS=8MHz No load, system HALT No load, system HALT 3/4 3/4 3/4 3/4 2.7 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2.565 3.2 3.6 3/4 4 8 3/4 3/4 3/4 3/4 1 2 1.4 2.1 2.700 3.3 3/4 3.6 3/4 3/4 3 5 1 7 3/4 3/4 3/4 3/4 2.835 3.4 24 Min. Typ. Max.
Ta=25C Unit V MHz MHz mA mA mA mA V V V V V V V
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Test Conditions Symbol ILDO IOL1 IOH1 IOL2 IOH2 IAUD RPH Parameter VDD LDO Output Current I/O Port Sink Current I/O Port Source Current PWM1/PWM2 Sink Current PWM1/PWM2 Sink Current AUD Source Current Pull-high Resistance 3/4 3V 3V 3V 3V 3V 3V Conditions VLDO_IN=5.5V VOL=0.1VDD VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD 3/4 60 7 -3.5 50 -14.5 3/4 20 100 3/4 3/4 3/4 3/4 -3 60 3/4 3/4 3/4 3/4 3/4 3/4 100 mA mA mA mA mA mA kW Min. Typ. Max. Unit
A.C. Characteristics
Test Conditions Symbol fSYS fTIMER tWDTOSC tWDT1 tWDT2 tRES tSST tINT Parameter VDD System Clock (RC OSC, Crystal OSC) Timer Inut Frequency Watchdog Oscillator Period Watchdog Time-out Period (WDT OSC) Watchdog Time-out Period (System Clock) External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width 3/4 3/4 3V 3V 3/4 3/4 3/4 3/4 Conditions 2.7V~3.6V 2.7V~3.6V 3/4 Without WDT prescaler Without WDT prescaler 3/4 Wake-up from HALT 3/4 4 0 45 12 3/4 1 3/4 1 3/4 3/4 90 23 1024 3/4 1024 3/4 8 8 180 45 3/4 3/4 3/4 3/4 Min. Typ. Max.
Ta=25C Unit
MHz MHz ms ms ms ms *tSYS ms
Note: *tSYS=1/fSYS
Characteristics Curves
* R vs. F Chart Characteristics Curves
R v s . F C h a rt
10 8 F re q u e n c y (M H z ) 6 3 .3 V 4 2 150 195 R 285 (k W ) 376 445
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* T vs. F Chart Characteristics Curves
T v s . F C h a rt
1 .0 6 1 .0 4 1 .0 2 (2 5 C )
SC
1 .0 0 0 .9 8 0 .9 6 0 .9 4 -4 0 -2 0 0
T (C )
V
DD
=3V
fO fO
SC
20
40
60
80
* V vs. F Chart Characteristics Curves - 3.0V
V v s . F C h a r t (F o r 3 .0 V )
10 9 8 7 6 8 M H z /1 5 0 k W
F re q u e n c y (M H z )
2 .7
3 .0 V
DD
3 .3 (V )
3 .6
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System Architecture
A key factor in the high-performance features of the Holtek range of Voice microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O, voltage type DAC, PWM direct drive output, capacitor/resistor sensor input and external RC oscillator converter with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from either a Crystal/ Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. When the RC oscillator is used, OSC2 can be used used as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of fSYS/4 with a 1:3 high/low duty cycle. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
O s c illa to r C lo c k ( S y s te m C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2
P ip e lin in g
F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ]
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7
NOP
Instruction Fetching
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Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL, that demand a jump to a non-consecutive Program Memory address. Note that the Program Counter width varies with the Program Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has 4 levels and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
P ro g ra m C o u n te r
T o p o f S ta c k S ta c k P o in te r B o tto m o f S ta c k
S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 S ta c k L e v e l 4 P ro g ra m M e m o ry
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
Program Counter Mode *10 Initial Reset Timer Base Overflow Timer Counter 0 Overflow Timer Counter 1 Overflow SIM Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 0 0 0 0 0 *9 0 0 0 0 0 *8 0 0 0 0 0 *7 0 0 0 0 0 *6 0 0 0 0 0 *5 0 0 0 0 0 *4 0 0 0 0 1 *3 0 0 1 1 0 *2 0 1 0 1 1 *1 0 0 0 0 0 *0 0 0 0 0 0
Program Counter + 2 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *10~*0: Program counter bits #10~#0: Instruction code bits S10~S0: Stack register bits @7~@0: PCL bits
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However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* Arithmetic operations ADD, ADDM, ADC, ADCM, * Location 004H
This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full.
* Location 008H
This vector is used by the 8-bit Timer 0. If a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Location 00CH
This vector is used by the 8-bit Timer1. If a overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full.
* Location 010H
Reserved.
* Location 014H
SUB, SUBM, SBC, SBCM, DAA
* Logic operations AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
* Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
* Increment and Decrement INCA, INC, DECA, DEC * Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA,
This vector is used by the SIM Bus interrupt service program. If the SIM Bus interrupt resulting from a slave address is matched or if 8 bits of data have been received or transmitted successfully from the I2C interface, or 8 bits of data have been received or transmitted successful from SPI interface, the program will jump to this location and begin execution if the interrupt is enabled and the stack is not full.
000H In itia lis a tio n V e c to r T im e B a s e In te rru p t V e c to r T im e r C o u n te r 0 In te rru p t V e c to r T im e r C o u n te r 1 In te rru p t V e c to r
SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code or program is stored. By using the appropriate programming tools, this Program memory device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming. Structure The program memory stores the program instructions that are to be executed. It also includes data, table and interrupt entries, addressed by the Program Counter along with the table pointer. The program memory size is 2K 15 bits. Certain locations in the program memory are reserved for special usage. Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
* Location 000H
004H 008H 00CH 010H 014H 015H 7FFH
S IM In te rru p t V e c to r
1 5 b its
Program Memory Structure
This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.
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Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, table pointers are used to setup the address of the data that is to be accessed from the Program Memory. However, as some devices possess only a low byte table pointer and other devices possess both a high and low byte pointer it should be noted that depending upon which device is used, accessing look-up table data is implemented in slightly different ways. There are two Table Pointer Registers known as TBLP and TBHP in which the lower order and higher order address of the look-up data to be retrieved must be respectively first written. The additional TBHP register allows the complete address of the look-up table to be defined and consequently allow table data from any address and any page to be directly accessed. For this device, after setting up both the low and high byte table pointers, the table data can then be retrieved from any area of Program Memory using the TABRDC [m] instruction or from the last page of the Program Memory using the TABRDL [m] instruction. When either of these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. The following diagram illustrates the addressing/data flow of the look-up table.
P ro g ra m C o u n te r H ig h B y te TBLP P ro g ra m M e m o ry
TBLH H ig h B y te o f T a b le C o n te n ts
S p e c ifie d b y [m ] Low B y te o f T a b le C o n te n ts
Look-up Table Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the devices. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is 700H which refers to the start address of the last page within the 204815-bit Program Memory of the microcontroller. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data table will be at the Program Memory address 706H or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRDC [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] instruction is executed.
tempreg1 db tempreg2 db : : mov a,06h mov tblp,a : : tabrdl
? ?
; temporary register #1 ; temporary register #2
; initialise table pointer - note that this address is referenced ; to the last page or present page
tempreg1
; ; ; ;
transfers value in table referenced by table pointer to tempregl data at prog. memory address 706H transferred to tempreg1 and TBLH
dec tblp tabrdl tempreg2
; reduce value of table pointer by one ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address 705H transferred to tempreg2 and TBLH in this example the data 1AH is transferred to tempreg1 and data 0FH to register tempreg2 the value 00H will be transferred to the high byte register TBLH
: : org 700h dc ; sets initial address of HT83F10/20/40/60/80 last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :
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Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Location Instruction *10 TABRDC [m] TABRDL [m] P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *10~*0: Current Program ROM table @7~@0: Write @7~@0 to TBLP pointer register P10~P8: Write P12~P8 to TBHP pointer register
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of RAM Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The Data Memory has a bank, known as Bank, which is implemented in 8-bit wide RAM. The RAM Data Memory is located in Bank 0 which is also subdivided into two sections, the Special Purpose Data Memory and the General Purpose Data Memory. The length of these sections is dictated by the type of microcontroller chosen. The start address of the RAM Data Memory for all devices is the address 00H, and the last Data Memory address is FFH. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address.
00H 2FH 30H
General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the SET [m].i and CLR [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory, is located in Bank, where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H.
S p e c ia l P u r p o s e D a ta M e m o ry G e n e ra l P u rp o s e D a ta M e m o ry (8 0 B y te s )
7FH
RAM Data Memory Structure Note: Most of the RAM Data Memory bits can be directly manipulated using the SET [m].i and CLR [m].i instructions with the exception of a few dedicated bits. The RAM Data Memory can also be accessed through the Memory Pointer registers MP. Rev. 1.00 11 May 12, 2009
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Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the RAM Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, watchdog, etc., as well as external functions such as I/O data control. The location of these registers within the RAM Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00H.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH IA R MP
Indirect Addressing Register - IAR The Indirect Addressing Register, IAR, although having location in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses the Indirect Addressing Register and Memory Pointer, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR register will result in no actual read or write operation to these register but rather to the memory location specified by their corresponding Memory Pointer, MP. Acting as a pair, IAR and MP can together only access data. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Register indirectly will return a result of 00H and writing to the registers indirectly will result in no operation. Memory Pointer - MP For all devices, Memory Pointer, known as MP is provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal register providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP, together with Indirect Addressing Register, IAR, are used to access data. Note that bit 7 of the Memory Pointers is not required to address the full memory space and will return a value of 1 if read.
ACC PCL TBLP TBLH W DTS STATUS IN T C TM R0 TM R0C TM R1 TM R1C PA PAC PB PBC
IN T C H S IM C S IM C S IM D S IM A R /S DAL DAH PW MC PW M PW M VOL H 0 IM C 2 R L R 1
:U nknow n
Special Purpose Data Memory Structure
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The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov loop: clr inc sdz jmp a,04h block,a a,offset adres1 mp,a IAR mp block loop ; setup size of block ; Accumulator loaded with first RAM address ; setup memory pointer with first RAM address ; clear the data at address defined by MP ; increment memory pointer ; check if last memory location has been cleared
continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the
INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Watchdog Timer Register - WDTS The Watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect Program Memory addresses. To implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. To provide variable Watchdog Timer reset times, the Watchdog Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register. By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT
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b7 TO PDF OV Z AC b0 C S T A T U S R e g is te r ith m e r r y fla x ilia r y r o fla g O v e r flo w g Ar Ca Au Ze tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g an n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 "
S y s te m M Pow erdow W a tc h d o g N o t im p le m
Status Register time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
* C is set if an operation results in a carry during an ad-
routine is entered to disable further interrupt and is set by executing the RETI instruction. Note: In situations where other interrupts may require servicing within present interrupt service routines, the EMI bit can be manually set by the program after the present interrupt service routine has been entered. Timer Registers All devices contain two 8-bit Timers whose associated registers are known as TMR0 and TMR1 which is the location where the associated timer's 8-bit value is located. Their associated control registers, known as TMR0C and TMR1C, contain the setup information for these timers. Note that all timer registers can be directly written to in order to preload their contents with fixed data to allow different time intervals to be setup. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB etc. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, etc., also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice-versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices. 14 May 12, 2009
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
* AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
* Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
* OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* PDF is cleared by a system power-up or executing the
CLR WDT instruction. PDF is set by executing the HALT instruction.
* TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Interrupt Control Register - INTC, INTCH Two 8-bit register, known as the INTC and INTCH registers, controls the operation of both external and internal timer interrupts. By setting various bits within these registers using standard bit manipulation instructions, the enable/disable function of the external and timer interrupts can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt
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Voice Control and Audio output Registers DAL, DAH, VOL The devices include a single 12-bit current type DAC function for driving an external 8W speaker through an external NPN transistor or Power Amplifier. The programmer must writer the voice data to these DAL/DAH registers. The programmer can control the DAC volume with 7-levels via the VOL register. Pulse Width Modulator Registers PWMC, PWML, PWMH Each device contains a single 12-bit PWM function for driving an external 8W speaker. The programmer must writer the voice data to PWML/PWMH register. The programmer can control the PWM volume with 8-levels via the VOL register. Serial Interface Module(SIM) Registers SIMC0, SIMC1, SIMAR/SIMC2, SIMDR Each SIM contains SPI and I2C function for communicating with other microcontroller or SPI Flash Memory. All devices contain an integrated I2C and SPI bus which interfaces to the external shared pins SDA ,SCL and SCSB ,SCK ,SDI ,SDO with PB on the microcontroller. The I2C correct setup and data transfer operation of this 2-line bidirectional bus utilizes 4 special function registers. The SIMAR register sets the slave address of the device while the SIMC0 is the control register that enables or disables the device as well as select whether it is in I2C or SPI mode. The SIMC1 register is the I2C status register while the SIMDR register is the input/output data register. The SPI correct setup and data transfer operation of this 3-line bidirectional bus utilizes 3 special function registers. The SIMC0 is the control register that enables or disables the device as well as select whether it is in I2C or SPI mode. The SIMC2 register is the SPI status register while the SIMDR register is the input/output data register. Memory and RAM Data Memory, the Flash Data Memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory. Accessing the Flash Data Memory The Flash Data Memory is accessed using a set of Macros in the library. These instructions control all functions of the Flash such as read, write, erase, enable etc. The internal Flash structure is similar to that of a standard SPI Flash Memory, for which 4 pins are used for transfer of instruction, address and data information. These are the Chip Select pin, CS, Serial Clock pin, SCK, Data In pin, SI and the Data Out pin, SO. All actions related to the Flash Memory must be conducted through each of these four Flash Memory download pins. By manipulating these four pin in the device, in accordance with the accompanying timing diagrams, the microcontroller can communicate with the Flash Memory and carry out the required read and write instructions. When reading data from the Flash Memory, CS should be set to 0 to start the data transmission. The data will clocked out on the rising edge of SCK and appear on SO. The SO pin will normally be in a high-impedance condition unless a READ statement is being executed. When writing to the Flash Memory the data must be presented first on SI and then clocked in on the rising edge of SCK. After all the instruction, address and data information has been transmitted, CS should be set to 1 to terminate the data transmission. Note that after power on the Flash Memory must be initialised as described. READ The READ instruction is used to read out one or more bytes of data from the Flash Data Memory. To instigate a READ instruction, the CS bit should be set low, followed by a command instruction and then the instruction code 03, all transmitted via the SI bit. The address information should then follow with the MSB being transmitted first. After the last address bit, A0, has been transmitted, the data can be clocked out, bit D7 first, on the rising edge of the SCK clock signal and can be read via the SO bit. The data information will first precede the reading of the first data bit, D7. After the full byte has been read out, the internal address will be automatically incremented allowing the next consecutive data byte to be read out without entering further address data. As long as the CS bit remains low, data bit D7 of the next address will automatically follow data bit D0 of the previous address being inserted between them. The address will keep incrementing in this way until CS returns to a high value. SO will normally be in a high impedance condition until the READ instruction is executed.
Flash Data Memory
The Data Memory is the location where the user Data is stored. For this device the Data Memory is a Flash type, which means it can be programmed and reprogrammed a large number of times, allowing the user the convenience of voice data modification using the same device. By using the appropriate programming tools, these devices offer users the flexibility to conveniently change and develop their applications while also offering a means of field programming. Flash Data Memory Structure The internal Flash Data Memory has a capacity of between 2M8 bit and 128K8 bit. Unlike the Program
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Read Data Byte Timing
Page Program Timing
Earse All Timing
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WRITE The WRITE instruction is used to write a page byte of data into the Flash Data Memory. To instigate a WRITE instruction, the CS bit should be set low, then the instruction code 02, all transmitted via the SI bit. For this device, The address information should then follow with the MSB bit being transmitted first. After the last address bit, A0, has been transmitted, the data can be immediately transmitted MSB first. After all the WRITE instruction code, address and data have been transmitted, the data will be written into the Flash Data Memory when the CS bit is set to high. The Flash Data Memory does this by executing an internal write-cycle, which will first erase and then write the previously transmitted data byte into the Flash Data Memory. This process takes place internally using the Flash Data Memorys own internal clock and does not require any action from the SCK clock. No further instructions can be accepted by the Flash Data Memory until this internal write-cycle has finished. Instruction READ WRITE ERAL Function Read Out Data Write Data Page Byte Erase All ERAL The ERAL instruction is used to erase the whole contents of the Flash Data Memory. After it has been executed all the data in the Flash Data Memory will be set to 1. To instigate this instruction, the CSB bit should be set low. The instruction code 20. Following on from this, a 20 should then be transmitted. After the ERAL instruction code has been transmitted, the Flash Data Memory data will be erased when the CS bit is set to high. The Flash Data Memory does this by executing an internal write-cycle. This process takes place internally using the Flash Data Memorys own internal clock and does not require any action from the SCK clock. No further instructions can be accepted by the Flash Data Memory until this internal write-cycle has finished. To determine when the write
Instruction Code 03 02 20 Instruction Set Summary
Address A23~A0 A23~A0 A23~A0
Data D7~D0 D7~D0 3/4
In Circuit Programming
The provision of Flash type Data Memory gives the user and designer the convenience of easy upgrades and modifications to their Data on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest data releases without removal and re-insertion of the device. Pin Name SI SO SCK CS VDD VSS Function Serial data input Serial data output Serial clock Signal Select Power supply Ground The Data Memory can be programmed serially in-circuit using a 8-wire interface. Data is downloaded and uploaded serially on two SI/SO pins with an additional line for the clock. Two additional lines are required for the power supply and one line for the select signal. The technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature.
C o n n e c to r D a ta In C lo c k E rro P ro o f S ig n a l S e le c t D a ta O u t Power G ro u n d R eset SO CLK NC CS SI VDD VSS R eset
In-circuit Programming Interface
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Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. Depending upon which device or package is chosen, the microcontroller range provides from 12 bidirectional input/output lines labeled with port names PA, PB, etc. These I/O ports are mapped to the Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selectable via configuration options and are implemented using a weak PMOS transistor. Note that if the pull-high option is selected, then all I/O pins on that port will be connected to pull-high resistors, individual pins can be selected for pull-high resistor options. Port A Wake-up Each device has a HALT instruction enabling the microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. After a HALT instruction forces the microcontroller into entering a HALT condition, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Note that each pin on Port A can be selected individually to have this wake-up feature. I/O Port Control Registers Each I/O port has its own control register PAC and PBC, to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a 1. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a 0, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control.
* Serial Interface Module
The device pins, PB0~PB3, are pin-shared with pins SDA, SCL, SCS, SCK, SDI, SDO. The choice of which function is used is selected using the SIMC0 register.
* I/O Pin Structures
The following diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. Note also that the specified pins refer to the largest device package, therefore not all pins specified will exist on all devices.
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Programming Considerations Within the user program, one of the first things to consider is port initialization. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the port control registers, PAC, PBC etc., are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA, PB, etc., are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
T1 S y s te m C lo c k T2 T3 T4 T1 T2 T3 T4
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.
V
DD
C o n tr o l B it D a ta B u s D CK S Q W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it Q D W r ite D a ta R e g is te r CK S Q M U X R e a d D a ta R e g is te r S y s te m W a k e -u p Q
P u ll- H ig h O p tio n
W eak P u ll- u p
PA0~PA7
W a k e - u p O p tio n
PA Input/Output Port
V C o n tr o l B it D a ta B u s D CK S W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it D W r ite D a ta R e g is te r CK S Q
M U X
DD
Q Q
P u ll- H ig h O p tio n
W eak P u ll- u p
Q
PB0 PB1 PB2 PB3
/S D /S C /S D /S C I S
O /S D A K /S C L
PB P B 0 /S P B 1 /S P B 2 /S D I, P
Da DO CK B3
ta /S /S /S
B it DA CL CS M
A n a lo g S w itc h O p tio n U X
R e a d D a ta R e g is te r
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Timers
The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. These devices contain two count up timers of 8-bit capacity. The provision of an internal prescaler to the clock circuitry of the timer gives added range to the timer. There are two types of register related to each Timer. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register retrieves the contents of the Timer. All devices can have the timer clock configured to come from the internal clock source. Configuring the Timer Input Clock Source The clock source for the 8-bit timers is the system clock divided by four. The 8-bit timer clock source is also first divided by a, the division ratio of which is conditioned by the three lower bits of the associated timer control register. Timer Registers - TMR0, TMR1 The timer registers are special function registers located in the special purpose Data Memory and is the place where the actual timer value is stored. All devices contain two 8-bit timers, whose registers are known as TMR0 and TMR1. The value in the timer registers increases by one each time an internal clock pulse is received. The timer will count from the initial value loaded by the preload register to the full count of FFH for the 8-bit timer at which point the timer overflows and an internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue counting. Note that to achieve a maximum full range count of FFH for the 8-bit timer, the preload registers must first be cleared to all zeros. It should be noted that after power-on, the preload registers will be in an unknown condition. Note that if the Timer Counters are in an OFF condition and data is written to their preload registers, this data will be immediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. Note also that when the timer registers are read, the timer clock will be blocked to avoid errors, however, as this may result in certain timing errors, programmers must take this into account. Timer Control Registers - TMR0C, TMR1C Each timer has its respective timer control register, known as TMR0C and TMR1C. It is the timer control register together with their corresponding timer registers that control the full operation of the timers. Before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization. Bits 7 and 6 of the Timer Control Register, must be set to the required logic levels. Bit 6 of the registers must always be wriiten with a 1, and bit 7 must always be written with a 0. The timer-on bit, which is bit 4 of the Timer Control Register and known as T0ON/ T1ON, depending upon which timer is used, provides the basic on/off control of the respective timer. setting the bit high allows the timer to run, clearing the bit stops the timer. For the 8-bit timers, which have prescalers, bits 0~2 of the Timer Control Register determines the division ratio of the input clock prescaler. Configuring the Timer The Timer is used to measure fixed time intervals, providing an internal interrupt signal each time the Timer overflows. To do this the Operating Mode Select bit pair in the Timer Control Register must be set to the correctvalue as shown. Control Register Operating Mode Select Bits Bit7 Bit6 1 0
The internal clock, fSYS, is used as the Timer clock. However, this clock source is further divided by a prescaler, the value of which is determined by the Prescaler Rate Select bits, which are bits 0~2 in the Timer Control Register. After the other bits in the Timer Control Register have been setup, the enable bit, which is bit 4 of the Timer Control Register, can be set high to enable the Timer to run. Each time an internal clock cycle occurs, the Timer increments by one. When it is full and overflows, an interrupt signal is generated and the Timer will
D a ta B u s P r e lo a d R e g is te r R e lo a d
T1PSC 2~T1PSC 0 T0PSC 2~T0PSC 0 fS /4 P r e s c a le r (1 /2 ~ 1 /2 5 6 )
T1TM 1 T0TM 1
T1TM 0 T0TM 0 T im e r T0O N T1O N 8 - B it C o u n te r O v e r flo w to In te rru p t
YS
T im e r M o d e C o n tr o l
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P r e s c a le r O u tp u t In c re m e n t T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+1
Timer Mode Timing Diagram
b7 TM 1 TM 0 TON PSC2 PSC1 b0 PSC0 T M R 0 C /T M R 1 C T im e r P r e s c a T0PSC 2 T0 T1PSC 2 T1 0 0 0 0 1 1 1 1 R e g is te r
le r R a te S e le c t T0PSC 0 PSC1 T1PSC 0 PSC1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1
T im e r 1 :2 1 :4 1 :8 1 :1 1 :3 1 :6 1 :1 1 :2 6 2 4
R a te
28 56
N o t im p le m e n t e d , r e a d a s " d o n 't c a r e " T im e r C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g M o d e S e le c t T0TM 0 T0TM 1 T1TM 0 T1TM 1 no 0 0 no 1 0 tim 0 1 1 1 no
m od m od erm m od
e a v a ila b le e a v a ila b le ode e a v a ila b le
Timer Control Register
reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer Interrupt Enable bit in the Interrupt Control Register, INTC, is reset to zero. Prescaler All of the 8-bit timers possess a prescaler. Bits 0~2 of their associated timer control register, define the pre-scaling stages of the internal clock source of the Timer. The Timer overflow signal can be used to generate signals for the Timer interrupt. Programming Considerations The internal system clock is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. In this mode, when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. When the Timer is read, the clock is blocked to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care
must be taken to ensure that the timers are properly initialized before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialized the timer can be turned on and off by controlling the enable bit in the timer control register.
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Timer Program Example The following example program section is based on the HT83F60 device, which contain two 8-bit timers. Programming the timer for other devices is conducted in a very similar way. The program shows how the timer registers are setup along with how the interrupts are enabled and managed. Points to note in the example are how, for the 8-bit timer. Note how the timer is turned on by setting bit 4 of the respective timer control register. The timer can be turned off in a similar way by clearing the same bit. This example program sets the timer to be in the timer mode which uses the internal fsys as their clock source, and produce a timer 0 interrupt per 1ms. #include HT83F60.inc jmp begin : org 04h ; reti org 08h ; jmp tmr0int ; org 0Ch reti org 10h reti org 14h reti : ; Tmr0int: : ; : reti : begin: ; mov a,06h ; mov tmr0,a ; mov a,094 ; mov tmr0c,a ; ; mov a,05h ; mov intc,a ;
time base vector timer 0 interrupt vector jump here when timer 0 overflows every 1ms
internal timer 0 interrupt routine
timer 0 main program placed here
setup timer 0 registers setup timer 0 low byte flow byte must be setup before high byte setup timer 0 control register setup timer mode and clock source is fsys/32 prescaler setup interrupt register enable global interrupt enable timer 0 interrupt
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Time Base
The Time Base function will generate a regular interrupt signal synchronised to the system clock which can be used by the application as a time base signal. Time Base Operation The Time Base operation is a very simple function for the generation of a regular time signal. This is implemented by generating a regular interrupt signal whose enable/disabled and request flags are in the INTC register. The clock source for the time base is the internal
S y s te m C lo c k /4
Time base Example The following example program section is based on the HT83F60 device. The program shows how the Time Base registers are setup along with how the interrupts are enabled and managed. The points to note in the example are how the Time Base is turned on by setting bit 4 of the INTC register. The Time Base can be turned off in a similar way by clearing the same bit. This example program sets the Time Base which uses the internal system clock as their clock source, and produces a time base interrupt every 0.5ms from a system source clock of 8MHz.
1024
O v e r flo w to In te rru p t
fSYS/4 clock source, which is then divided internally by a value of 1024. It is this divided signal that generates the internal interrupt. The Time Base Interrupt is enabled by the ETBI bit in the INTC register and interrupt request flag is the TBF flag in the same register. A time base of 1ms will therefor be generated from a system clock of 4MHz and a time base of 0.5ms will be generated from a system clock source of 8MHz.
#include HT83F60.inc jmp begin : org 04h jmp time_base_int org 08h reti org 0Ch reti org 10h reti org 14h reti : time_base_int: :
; time base vector ; jump here when time base overflows per 0.5ms
; time base interrupt routine
; time base main program placed here : reti : begin: mov mov a,03h intc,a ; setup interrupt register ; enable global and time base interrupt ; enable time base
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Serial Interface
The device contains both SPI and I C serial interface functions, which allows two methods of easy communication with external peripheral hardware. As the SPI and I2C function share the same external pins and internal registers their function must first be chosen by selecting the correct configuration option. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices.
* SPI Interface Operation
2
Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with segment pins and with the I2C function pins, the SPI interface must first be enabled by selecting the correct configuration option. After the SPI configuration option has been selected it can then also be selected using the SIMEN bit in the SIMC0 register. The SPI function in this device offers the following features:

Full duplex synchronous data transfer Both Master and Slave modes LSB first or MSB first data transmission modes Transmission complete flag
Several other configuration options also exist to setup various SPI interface options as follows:

The SPI interface is a full duplex synchronous serial data link. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. Multiple slave devices can be connected to the SPI serial bus with each device controlled using its slave select line. The SPI is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and
SPI pin enabled WCOL bit enabled or disabled CSEN bit enabled or disabled The status of the SPI interface pins is determined by a number of factors, whether the device is in master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN.
D a ta B u s S IM D R ( R e c e iv e d D a ta R e g is te r )
D7D6D5D4D3D2D1D0 M
U X
SDO
B u ffe r S IM E N
SDO
M LS M U X M U X C0C1C2 In te r n a l B a u d R a te C lo c k SCK EN a n d , s ta rt C lo c k P o la r ity a n d , s ta rt SDI
TRF AND W C O L F la g
M a s te r o r S la v e S IM E N In te r n a l B u s y F la g S IM E N
W r ite S B D R E n a b le /D is a b le
a n d , s ta rt EN
W r ite S IM D R W r ite S IM D R
SCS
M a s te r o r S la v e S IM E N CSEN
Block Diagram
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Master (SIMEN=1) Master/Salve (SIMEN=0) SCS SDO SDI SCK Z Z Z Z CSEN=1 L O I, Z L(CPOL=1) H(CPOL=0) CSEN=0 Z O I, Z L(CPOL=1) H(CPOL=0) CSEN=0 Z O I, Z I, Z Slave (SIMEN=1) SCS line=0 (CSEN=1) I, Z O I, Z I, Z SCS line=1 (CSEN=1) I, Z Z Z Z
Z floating, H output high, L output low, I Input, Ooutput level, I,Z input floating (no pull-high) SPI Interface Pin Status
* SPI Registers
The SIMDR register is used to store the data being transmitted and received. There are two control registers associated with the SPI interface, SIMC0 and SIMC2 and one data register known as SIMDR. The SIMC1 register is not used by the SPI function. Register SIMC0 is used to control the enable/disable function, the power down control and to set the data transmission clock frequency. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc. The following gives further explanation of each bit:
WCOL The WCOL bit is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SMDR register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Note that using the CSEN bit can be disabled or enabled via configuration option. CSEN The CSEN bit is used as an on/off control for the SCS pin. If this bit is low then the SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS pin will be enabled and used as a select pin. MLS The MLS is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Note that the SIMC2 register is the same as the SIMAR register used by the I2C interface.
SIMEN The SIMEN bit is the overall on/off control for the SPI interface. When the SIMENbit is cleared to zero to disable the SPI interface, the SDI, SDO, SCK and SCS lines will be in a floating condition and the SPI operating current will be reduced to <0.1mA at 5V. When the bit is high the SPI interface is enabled. Note that when the SIMEN bit changes from low to high the contents of the SPI control registers will be in an unknown condition and should therefore be initialised by the application program. SIM0~SIM2 These three bits control the Master/Slave selection and also setup the SPI interface clock speed when in the Master Mode. The SPI clock is a function of the system clock whether it be RC type or Crystal type. If the Slave Mode is selected then the clock will be supplied by the external Master device. The following gives further explanation of each bit: TRF The TRF bit is the Transmit/Receive Complete flag and is cleared by the application program and can be used to generate an interrupt. When the bit is high the data has been transmitted or received. If the bit is low the data is being transmitted or has not yet been received.
* SPI Communication
After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMDR register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMDR register will be transmitted and any data on the SDI pin will be shifted into the SIMDR register. The master should output an SCS signal before a clock signal is provided and slave data transfers should be enabled/disabled before/after an SCS signal is received.
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S IM E N = 1 , C S E N = 0 a n d w r ite d a ta to S IM D R ( if p u lle d h ig h ) SCS
SCK SDI SDO SCK D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S IM E N = C S E N = 1 a n d w r ite d a ta to S IM D R
SPI Interface Timing
b7 S IM 2
b0 S IM 1 S IM 0 S IM E N S IM C 0 R e g is te r N o t im p le m e n te d , r e a d a s " 0 " S P I O n /O ff c o n tro l 1 : e n a b le 0 : d is a b le N o t im p le m e n te d S P I M a s te r /S la v e a n d C lo c k S IM 2 S IM 1 S IM 0 0 0 m as 0 0 0 m as 1 1 0 0 m as 1 0 m as 1 0 1 Res 0 0 1 Res 1 1 1 Res 0 1 1 Res 1 C o n tro l te te te te r, r, r, r, e e e e fS fS fS fS d d d d
YS YS YS YS
/4
/1 6 /6 4
e rv e rv e rv e rv
SPI Control Register - SIMC0
b7 CKPOL CKEG M LS CSEN W COL
b0 TRF S IM C 2 R e g is te r T r a n s m it/R e c e iv e c o m p le te fla g 1 : d a ta tr a n s fe r c o m p le te 0 : d a ta tr a n s fe r in c o m p le te W r ite c o llis io n fla g 1 : d a ta c o llis io n 0 : n o c o llis io n S C S p in e n a b le 1 : e n a b le 0 : d is a b le , S C S flo a tin g D a ta s h ift o r d e r 1 : M S B fir s t 0 : L S B fir s t S P I c lo c k e d g e s e le c tio n 1 : fa llin g e d g e 0 : r is in g e d g e S P I c lo c k p o la r ity s e le c tio n 1 : lo w le v e l 0 : h ig h le v e l N o t im p le m e n te d , r e a d a s " 0 "
SPI Control Register - SIMC2
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A S P I tra n s fe r C le a r W C O L
W r ite D a ta in to S IM D R
m a s te r
m a s te r o r s la v e
s la v e Y W CO L=1?
S IM [2 :0 ]= 0 0 0 , 0 0 1 ,0 1 0 ,0 1 1
S IM [2 :0 ]= 1 0 1
N c o n fig u r e C SEN and M LS
T r a n s m is s io n c o m p le te d ? (T R F = 1 ? )
S IM E N = 1
Y R e a d D a ta fro m S IM D R
A
C le a r T R F
T ra n s fe r F in is h e d ?
N
Y END
SPI Transfer Control Flowchart
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I2C Interface The I C bus is a bidirectional 2-line communication interface originally developed by Philips. The possibility of transmitting and receiving data on only 2 lines offers many new application possibilities for microcontroller based applications.
* I2C Interface Operation
2
As the I2C interface pins are pin-shared with segment pins and with the SPI function pins, the I2C interface must first be enabled by selecting the correct configuration option. There are two lines associated with the I2C bus, the first is known as SDA and is the Serial Data line, the second is known as SCL line and is the Serial Clock line. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For this device, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode.
* I2C Registers
The SIMDR register is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMDR register. After the data is received from the I2C bus, the microcontroller can read it from the SIMDR register. Any transmission of data to the I2C bus or reception of data from the I2C bus must be made via the SIMDR register. The SIMAR register is the location where the slave address of the microcontroller is stored. Bits 1~7 of the SIMAR register define the microcontroller slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMAR register, the microcontroller slave device will be selected. Note that the SIMAR register is the same register as SIMC2 which is used by the SPI interface. The SIMC0 register is used for the I2C overall on/off control.
* I2C Configuration Option
There are several configuration options associated with the I2C interface. One of these is to enable the RNIC bit function which selects the RNIC bit in SIMC1 register. Another configuration option determines the debounce time of the I2C interface. This add a debounce delay time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time if selected can be chosen to be either 1 or 2 system clocks.
There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMAR and one data register, SIMDR.
b7 SA6
b0 SA5 SA4 SA3 SA2 SA1 SA0 S IM A R R e g is te r N o t im p le m e n te d , r e a d a s " 0 " I2C d e v ic e s la v e a d d r e s s
Slave Address Register - SIMAR
b7 S IM 2
b0 S IM 1 S IM 0 S IM E N S IM C 0 R e g is te r N o t im p le m e n te d , r e a d a s " 0 " I2C O n /O ff c o n tro l 1 : e n a b le 0 : d is a b le N o t im p le m e n te d I2 C M a s te r /S la v e a n d c lo c k S IM 2 S IM 1 S IM 0 0 0 0 No 1 0 0 No 0 1 0 No 1 1 0 No 0 0 1 No 1 0 1 No 0 1 1 I2C 1 1 1 No c o n tro l tus tus tus tus tus tus mo tus ed ed ed ed ed ed de ed
I2C Control Register - SIMC0 Rev. 1.00 28 May 12, 2009
HT83FXX
b7 HCF b0 HAAS HBB HTX TXAK SRW R N IC RXAK S IM C 1 R e g is te r R e c e iv e a c k n o w le d g e fla g 1 : n o t a c k n o w le d g e d 0 : a c k n o w le d g e d I2 C r u n in g c lo c k 1 : I2 C r u n in g is n o t u s in g in te r n a l c lo c k 0 : I2 C r u n in g is u s in g in te r n a l c lo c k M a s te r d a ta r e a d /w r ite r e q u e s t fla g 1 : re q u e s t d a ta re a d 0 : r e q u e s t d a ta w r ite T r a n s m it a c k n o w le d g e fla g 1 : d o n 't a c k n o w le d g e 0 : a c k n o w le d g e T r a n s m it/R e c e iv e m o d e 1 : tr a n s m it m o d e 0 : r e c e iv e m o d e I2 C b u s b u s fla g 1:busy 0:notbusy C a llin g a d d r e s s m a tc h e d fla g 1 : m a tc h e d 0 : n o t m a tc h e d D a ta tr a n s fe r fla g 1 : tr a n s fe r c o m p le te 0 : tr a n s fe r n o t c o m p le te
I2C Control Register - SIMC1 The following gives further explanation of each bit:

SIMEN The SIMEN bit determines if the I2C bus is enabled or disabled. If data is to be transferred or received on the I2C bus then this bit must be set high. The following gives further explanation of each bit:
HCF The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. HASS The HASS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. HBB The HBB flag is the I2C busy flag. This flag will be high when the I2C bus is busy which will occur when a START signal is detected. The flag will be reset to zero when the bus is free which will occur when a STOP signal is detected. HTX The HTX flag is the transmit/receive mode bit. This flag should be set high to set the transmit mode and low for the receive mode. TXAK The TXAK flag is the transmit acknowledge flag. After the receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock. To continue receiving more data, this bit has to be reset to zero before further data is received. 29
SRW The SRW bit is the Slave Read/Write bit. This bit determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address match, that is when the HAAS bit is set high, the device will check the SRW bit to determine whether it should be in transmit mode or receive mode. If the SRW bit is high, the master is requesting to read data from the bus, so the device should be in transmit mode. When the SRW bit is zero, the master will write data to the bus, therefore the device should be in receive mode to read this data. RNIC The RNIC bit is used as I2C running clock from Internal or external clock. If this bit is low then I2C running using internal clock and it will not wake-up when I2C interrupts in the Power Down Mode. If the bit is high I2C running using external clock and it will wake-up when I2C interrupts in the Power Down Mode. RXAK The RXAK flag is the receive acknowledge flag. When the RXAK bit has been reset to zero it means that a correct acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When in the transmit mode, the transmitter checks the RXAK bit to determine if the receiver wishes to receive the next byte. The transmitter will therefore continue sending out data until the RXAK bit is set to 1. When this occurs, the transmitter will release the SDA line to allow the master to send a STOP signal to release the bus.

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S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r
I2C Bus Communication Communication on the I C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the microcontroller matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the microcontroller slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the microcontroller to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: Step 1 Write the slave address of the microcontroller to the I2C bus address register SIMAR. Step 2 Set the SIMEN bit in the SIMC0 register to 1 to enable the I2C bus. Step 3 Set the EHI bit of the interrupt control register to enable the I2C bus interrupt.
2
* Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by the microcontroller, which is only a slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high.
* Slave Address
The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The microcontroller slave device will also set the status flag HAAS when the addresses match. As an I2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMDR register, or in the receive mode where it must implement a dummy read from the SIMDR register to release the SCL line.
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SCL S ta rt S la v e A d d r e s s SRW ACK
SDA
1
0
1 1
0
1
0
1
0
SCL
D a ta
ACK
S to p
1 SDA S=S SA= SR= M =S D=D A=A P=S S ta rt (1 S la v e SRW la v e d a ta (8 C K (R to p (1 SA
0
0
1
0
1
0
0
b it) A d d r e s s ( 7 b its ) b it ( 1 b it) e v ic e s e n d a c k n o w le d g e b it ( 1 b it) b its ) X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it) b it) SR M D A D
2
A S
SA
SR
M
D
A D
A
P
I C Communication Timing Diagram
* SRW Bit
The SRW bit in the SIMC1 register defines whether the microcontroller slave device wishes to read data from the I2C bus or write data to the I2C bus. The microcontroller should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW bit is set to 1 then this indicates that the master wishes to re a d dat a f r o m t h e I 2 C bus , t h e r ef o r e t h e microcontroller slave device must be setup to send data to the I2C bus as a transmitter. If the SRW bit is 0 then this indicates that the master wishes to send data to the I2C bus, therefore the microcontroller slave device must be setup to read data from the I2C bus as a receiver.
* Acknowledge Bit
the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level 0, before it can receive the next data byte. If the transmitter does not receive an acknowledge bit signal from the receiver, then it will release the SDA line and the master will send out a STOP signal to release control of the I2C bus. The corresponding data will be stored in the SIMDR register. If setup as a transmitter, the microcontroller slave device must first write the data to be transmitted into the SIMDR register. If setup as a receiver, the microcontroller slave device must read the transmitted data from the SIMDR register.
SCL SDA
After the master has transmitted a calling address, any slave device on the I2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. This acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS bit is high, the addresses have matched and the microcontroller slave device must check the SRW bit to determine if it is to be a transmitter or a receiver. If the SRW bit is high, the microcontroller slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to 1 if the SRW bit is low then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to 0.
* Data Byte
S ta r t b it
D a ta s ta b le
D a ta a llo w change
S to p b it
Data Timing Diagram
* Receive Acknowledge Bit
When the receiver wishes to continue to receive the next data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The microcontroller slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master.
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is
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S ta rt
No
HAAS=1 ? Yes Yes
Yes No
No
HTX=1 ?
SRW =1 ?
R e a d fro m S IM D R
SET HTX
C LR H TX C LR TXAK
RETI Yes RXAK=1 ? No C LR H TX C LR TXAK W r ite to S IM D R
W r ite to S IM D R
D um m y R ead F ro m S IM D R
RETI
RETI
D um m y R ead fro m S IM D R
RETI
RETI
I2C Bus ISR Flow Chart
S ta rt
W r ite S la v e A d d re s s to S IM A R
S E T S IM [2 :0 ]= 1 1 0 S E T S IM E N
D is a b le C L R E S IM I P o ll S IM F to d e c id e w h e n to g o to I2C B u s IS R
I2C B u s In te rru p t= ?
E n a b le
S E T E S IM I W a it fo r In te r r u p t
G o to M a in P r o g r a m
G o to M a in P r o g r a m
I2C Bus Initialisation Flow Chart
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HT83FXX
Interrupts
Interrupts are an important part of any microcontroller system. When an internal function such as a Time Base or Timer requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. Each device contains a Time Base interrupt and two internal timer interrupt functions. The Time Base interrupt is controlled by bit 1 of INTC register, while the internal interrupt is controlled by the Timer Counter overflow. Interrupt Register Overall interrupt control, which means interrupt enabling and flag setting, is controlled using two registers, known as INTC and INTCH, which are located in the Data Memory. By controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Operation A timer or Time Base overflow or by setting their corresponding request flag, if their appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will take program execution to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagram with their order of priority. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full.
b7 T1F T0F TBF ET1 ET0 ETBI
b0 EMI IN T C R e g is te r M a s te r In te r r u p t G lo b a l E n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le T im e B a s e In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e r 0 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e r 1 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e B a s e In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r 0 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r 1 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o im p le m e n te d , r e a d a s " 0 "
Interrupt Control Register
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b7 S IF E S II b0 IN T C H R e g is te r N o im p le m e n te d , r e a d a s " 0 " C o n tr o l s e r ia l in te r fa c e in te r r u p t 1 : e n a b le 0 : d is a b le N o im p le m e n te d , r e a d a s " 0 " S e r ia l in te r fa c e in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e N o im p le m e n te d , r e a d a s " 0 "
INTCH Register
A u to m a tic a lly C le a r e d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e T im e B a s e R e q u e s t F la g E IF T im e r 0 In te r r u p t R e q u e s t F la g T 0 F T im e r 1 In te r r u p t R e q u e s t F la g T 1 F S IM In te r r u p t R e q u e s t F la g S IF EEI
A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly P r io r ity EMI H ig h
ET0 In te rru p t P o llin g
ET1
E S II
Low
Interrupt Structure
Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the accompanying table shows the priority that is applied. Interrupt Source Time Base Interrupt Timer 0 Overflow Timer 1 Overflow SIM Interrupt Interrupt Vector 04H 08H 0CH 14H HT83FXX Priority 1 2 3 4
Time Base Interrupt Each device contains a Time Base whose corresponding interrupt enable bits are known as ETBI and is located in the INTC register. For a Time Base generated interrupt to occur, the corresponding Time Base interrupt enable bit must be first set. Time Base also has a corresponding Time Base interrupt request flag, which is known as TBF, also located in the INTC register. When the master interrupt and corresponding timer interrupt enable bits are enabled, the stack is not full, and when the corresponding timer overflows a subroutine call to the corresponding Time Base interrupt vector will occur. The corresponding Program Memory vector locations for the Time Base is 04H. After entering the interrupt execution routine, the corresponding interrupt request flag, TBF will be reset and the EMI bit will be cleared to disable other interrupts.
Suitable masking of the individual interrupts using the INTC and INTCH registers can prevent simultaneous occurrences.
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Timer Interrupt For a timer generated interrupt to occur, the corresponding timer interrupt enable bit must be first set. Each device contains two 8-bit timers whose corresponding interrupt enable bits are known as ET0 and ET1and are located in the INTC register. Each timer also has a corresponding timer interrupt request flag, which are known as T0F and T1F, also located in the INTC register. When the master interrupt and corresponding timer interrupt enable bits are enabled, the stack is not full, and when the corresponding timer overflows a subroutine call to the corresponding timer interrupt vector will occur. The corresponding Program Memory vector locations for Timer 0 and Timer1 are 08H and 0CH. After entering the interrupt execution routine, the corresponding interrupt request flags, T0F or T1F will be reset and the EMI bit will be cleared to disable other interrupts. Serial Interface Module - SIM - Interrupt SIM Interrupts include both the SPI and I C Interrupts. The SIM Mode is determined by the SIM2, SIM1 and SIM0 bits in the SIMC0 register. For a SPI Interrupt to occur, the global interrupt enable bit, EMI, and the corresponding SIM interrupt enable bit, ESII, must be first set. The SIMEN bit in the SIMC0 register must also be set. An actual SPI Interrupt will take place when the flag, SIF, is set, a situation that will occur when 8-bits of data are transferred or received from either of the SPI interfaces. When the interrupt is enabled, the stack is not full and an SIM interrupt occurs, a subroutine call to the SIM interrupt vector at location 14H, will take place. When the interrupt is serviced, the SPI interrupt request flag, SIF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
2
For an I2C interrupt to occur, the corresponding interrupt enable bit ESII must be first set. An actual I2C interrupt will be initialized when the SIM interrupt request flag, SIF, is set, a situation that will occur when a matching I2C slave address is received or from the completion of an I2C data byte transfer. When the interrupt is enabled, the stack is not full and a SIM interrupt occurs, a subroutine call to the SIM interrupt vector at location 14H, will 2 take place When an I C interrupt occurs, the interrupt request flag SIF will be reset and the EMI bit will be cleared to disable other interrupts. Programming Considerations By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the INTC or INTCH register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the CALL subroutine instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance.
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Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* Power-on Reset
10kW
VDD RES S S T T im e - o u t In te rn a l R e s e t
0 .9 V tR
DD
STD
Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.
VDD 100kW RES 0 .1 m F VSS
Basic Reset Circuit For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F 100kW RES VDD
0 .1 m F VSS
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.
Enhanced Reset Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website.
* RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point.
RES S S T T im e - o u t In te rn a l R e s e t 0 .4 V 0 .9 V
DD DD
tR
STD
RES Reset Timing Chart
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* Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t
The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting All Timer will be turned off The Timer Prescaler will be cleared I/O ports will be setup as inputs Stack Pointer will point to the top of the stack
tR
S S T T im e - o u t In te rn a l R e s e t
STD
Program Counter Interrupts WDT Timer Prescaler
WDT Time-out Reset during Normal Operation Timing Chart
* Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
Input/Output Ports Stack Pointer
tS
S S T T im e - o u t
ST
WDT Time-out Reset during Power Down Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 u 1 1 0 u u 1 RESET Conditions RES reset during power-on RES or LVR reset during normal operation WDT time-out reset during normal operation WDT time-out reset during Power Down
Note: u stands for unchanged
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The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Register MP ACC PCL TBLP TBLH WDTS STATUS INTC TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC INTCH SIMC0 SIMC1 SIMDR SIMAR/ SIMC2 DAL DAH PWMCR PWML PWMH VOL Reset (Power-on) -xxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 0000 0111
--00 xxxx
WDT Time-out RES Reset (Normal Operation) (Normal Operation) -uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 -- 1u uuuu -000 0000 0000 0000 0100 0000 0000 0000 0100 0000 1111 1111 1111 1111 ---- 1111 ---- 1111
--00 --00
RES Reset (HALT) -uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 -- 01 uuuu -000 0000 0000 0000 0100 0000 0000 0000 0100 0000 1111 1111 1111 1111 ---- 1111 ---- 1111
--00 --00
WDT Time-out from HALT -uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu
--uu --uu
-uuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu -000 0000 0000 0000 0100 0000 0000 0000 0100 0000 1111 1111 1111 1111 ---- 1111 ---- 1111
--00 --00
-000 0000 0000 0000 0100 0000 0000 0000 0100 0000 1111 1111 1111 1111 ---- 1111 ---- 1111
--00 --00
111- --0100- -0-1 xxxx xxxx 0000 0000 xxxx ---xxxx xxxx 0--- 0000 xxxx ---xxxx xxxx xxxx -xxx
111- --0100- -0-1 xxxx xxxx 0000 0000 uuuu ---uuuu uuuu 0--- 0000 uuuu ---uuuu uuuu uuuu -uuu
111- --0100- -0-1 xxxx xxxx 0000 0000 uuuu ---uuuu uuuu 0--- 0000 uuuu ---uuuu uuuu uuuu -uuu
111- --0100- -0-1 xxxx xxxx 0000 0000 uuuu ---uuuu uuuu 0--- 0000 uuuu ---uuuu uuuu uuuu -uuu
uuu- --uuuu- -u-u xxxx xxxx uuuu uuuu uuuu ---uuuu uuuu u--- uuuu uuuu ---uuuu uuuu uuuu -uuu
Note: u stands for unchanged x stands for unknown - stands for undefined
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Oscillator
Various oscillator options offer the user a wide range of functions according to their various application requirements. Two types of system clocks can be selected while various clock source options for the Watchdog Timer are provided for maximum flexibility. All oscillator options are selected through the configuration options. The two methods of generating the system clock are:
* External crystal/resonator oscillator * External RC oscillator
External RC Oscillator Using the external system RC oscillator requires that a resistor, with a value between 150kW and 300kW, is connected between OSC1 and VSS. The generated system clock divided by 4 will be provided on OSC2 as an output which can be used for external synchronization purposes. Note that as the OSC2 output is an NMOS open-drain type, a pull high resistor should be connected if it to be used to monitor the internal frequency. Although this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD, temperature and process variations and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are required. For the value of the external resistor ROSC refer to the Holtek website for typical RC Oscillator vs. Temperature and VDD characteristics graphics. Note that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. The external capacitor shown on the diagram does not influence the frequency of oscillation.
OSC1 R fS
YS OSC
One of these two methods must be selected using the configuration options. More information regarding the oscillator is located in Application Note HA0075E on the Holtek website. External Crystal/Resonator Oscillator The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation
C1 Rp In te r n a l O s c illa to r C ir c u it
OSC1 Rf Ca
/4 N M O S O p e n D r a in
OSC2
External RC Oscillator
Cb C2 OSC2
T o in te r n a l c ir c u its
Watchdog Timer Oscillator The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 65ms at 5V requiring no external components. When the device enters the Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option.
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . 2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator with the crystal or resonator manufacturers specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to assist with oscillation start up. Internal Ca, Cb, Rf Typical Values @ 5V, 25C Ca 11~13pF Cb 13~15pF Rf 800kW
Oscillator Internal Component Values
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Power Down Mode and Wake-up
Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode, also known as the HALT Mode or Sleep Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* The system oscillator will stop running and the appli-
Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling edge on Port A * A system interrupt * A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled. No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended.
cation program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
their present condition.
* The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT oscillator. The WDT will stop if its clock source originates from the system clock.
* The I/O ports will maintain their present condition. * In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. Care must also be taken with the loads, which are connected to I/Os, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the Watchdog Timer internal oscillator.
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Low Drop Output - LDO
All device include a fully integrated LDO regulator which can be used to provide a fixed voltage for user applications. The integrated LDO is a simple three terminal device with an external input pin, LDO_IN, external output pin, LDO_OUT, and a ground pin connected to the device VSS pin. Implemented in CMOS technology, it can deliver a 100mA output current and allow an input voltage as high as 24V. It will supply a fixed output voltage level of 3.3V. Using CMOS technology ensures that the regulator has a low dropout voltage and a low quiescent current. period of 17ms. Note that this period can vary with VDD, temperature and process variations. For longer WDT time-out periods the WDT prescaler can be utilized. By writing the required value to bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2, longer time-out periods can be achieved. With WS0, WS1 and WS2 all equal to 1, the division ratio is 1:128 which gives a maximum time-out period of about 2.1s. A configuration option can select the instruction clock, which is the system clock divided by 4, as the WDT clock source instead of the internal WDT oscillator. If the instruction clock is used as the clock source, it must be noted that when the system enters the Power Down Mode, as the system clock is stopped, then the WDT clock source will also be stopped. Therefore the WDT will lose its protecting purposes. In such cases the system cannot be restarted by the WDT and can only be restarted using external signals. For systems that operate in noisy environments, using the internal WDT oscillator is therefore the recommended choice. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a WDT time-out occurs, only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the WDT and the WDT prescaler. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a HALT instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single CLR WDT instruction while the second is to use the two commands CLR WDT1 and CLR WDT2. For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both CLR WDT1 and CLR WDT2 must both be executed to successfully clear the WDT. Note that for this second option, if CLR WDT1 is used to clear the WDT, successive executions of this instruction will have no effect, only the execution of a CLR WDT2 instruction will clear the WDT. Similarly, after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer.
Low Voltage Detector - LVD
The Low Voltage Detector internal function provides a means for the user to monitor when the power supply voltage falls below a certain fixed level as specified in the DC characteristics. Operation The Low Voltage Detector must first be enabled using a configuration option. The LVD control bit is bit 2 of the PWMCR regsiter and is known as LVDF. Under normal operation, and when the power supply voltage is above the specified VLVD value in the DC characteristic section, the LVDF bit will remain at a zero value. If the power supply voltage should fall below this VLVD value then the LVDF bit will change to a high value indicating a low voltage condition. Note that the LVDF bit is a read-only bit. By polling the LVDF bit in the PWMCR register, the application program can therefore determine the presence of a low voltage condition.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT clock is supplied by one of two sources selected by configuration option: its own self-contained dedicated internal WDT oscillator, or the instruction clock which is the system clock divided by 4. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation. The internal WDT oscillator has an approximate period of 65ms at a supply voltage of 5V. If selected, it is first divided by 256 via an 8-stage counter to give a nominal
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b7 W S2 W S1 b0 W S0 W D T S R e g is te r W D T p r e s c a le r r a te s e le c t W DTR W S0 W S1 W S2 1 :1 0 0 0 1 :2 1 0 0 1 :4 0 1 0 1 :8 1 1 0 1 :1 0 0 1 1 :3 1 0 1 1 :6 0 1 1 1 :1 1 1 1 2 4 N otused a te
6 28
Watchdog Timer Register
CLR CLR
W D T 1 F la g W D T 2 F la g
C le a r W D T T y p e C o n fig u r a tio n O p tio n CLR W D T C lo c k S o u r c e C o n fig u r a tio n O p tio n 8 - b it C o u n te r ( 2 5 6 )
1 o r 2 In s tr u c tio n s fS
YS
/4
CLR 7 - b it P r e s c a le r
W D T O s c illa to r W D T C lo c k S o u r c e
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
Voice Output
The device contains an internal 12-bit DAC function which can be used for audio signal generation. Voice Control Two internal registers DAL and DAH contain the 12-bit digital value for conversion by the internal DAC. There is also a DAC enable/disable control bit in the PWMC control register for overall on/off control of the DAC circuit. If the DAC circuit is not enabled, the the DAH/DAL value outputs will be invalid. Writing a 1 to the DAC bit in bit1 of PWMCR will enable the enable DAC circuit, while writing a 0 to the DAC bit will disable the DAC circuit. Audio Output and Volume Control - DAL, DAH, VOL The audio output is 12-bits wide whose highest 8-bits are written into the DAH register and whose lowest four bits are written into the highest four bits of the DAL register. Bits 0~3 of the DAL register are always read as zero. There are 8 levels of volume which are setup using the VOL register. Only the highest 3-bits of this register are used for volume control, the other bits are not used and read as zero.
D A L R e g is te r
b7 D11 D10 D9 D8 D7 D6 D5 b0 D4 D A H R e g is te r A u d io o u tp u t b7 D3 D2 D1 D0 b0 D A L R e g is te r N o t u s e d , re a d a s "0 " A u d io o u tp u t
DAH
b7
V2
R e g is te r
b0
V1 V0
V O L R e g is te r U sed by P W M o u tp u t N o t u s e d , re a d a s "0 " D A C v o lu m e c o n tr o l d a ta
V o ic e C o n tr o l R e g is te r
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Pulse Width Modulation Output
All devices include a single 12-bit PWM function which can directly drive external audio components such as speakers. Pulse Width Modulator Operation The PWM output is provided on two complimentary outputs on the PWM1 and PWM2 pins, providing a differential output pair and thus capable of higher drive power. These two pins can directly drive a piezo buzzer or an 8 ohm speaker without using external components. The PWM outputs can also be used single ended, where the signal is provided on the PWM1 output, and again can also be used by itself alone to drive a piezo buzzer or an 8 ohm speaker without external components. This single end output drive type is chosen using the Single_PWM bit in the PWMCR register. If the MSB_SIGN bit is low, then the signal that is provided on PWM1and PWM2 will obtain a GND level voltage after setting the PWMCC bit high. If the MSB_SIGN bit is high, then the signal that is provided on PWM2 and PWM1 will have a GND level voltage when the PWMCC bit is set high.
PW M1 PW M2 0 .0 1 m F * 0 .0 1 m F *
The two PWM outputs will initially be at low levels, and if the PWM function is stopped will also return to a low level. If the PWMCC bit changes from low to high then the PWM function will start running and latch new data. If the data is not updated then the old value will remain. If the PWMCC bit changes from high to low, at the end of the duty cycle, the PWM output will stop.
b7 P3 P2 P1 P0 b0 P W M L R e g is te r N o t u s e d , re a d a s "0 " PW M o u tp u t
P u ls e W id th M o d u la to r D a ta L o w
b7 P11 P10 P9 P8 P7 P6 P5 b0 P4
R e g is te r
R e g is te r o u tp u t
PW MH PW M
P u ls e W id th M o d u la to r D a ta H ig h R e g is te r
b7
VO L3VO L2VO L1VO L0
b0 V O L R e g is te r PW M v o lu m e c o n tr o l d a ta N o t u s e d , re a d a s "0 " U s e d b y a u d io o u tp u t
V o ic e C o n tr o l R e g is te r
S peaker
N o te : " * " F o r r e d u c in g th e d ig ita l n o is e th a t P W M m a y c a u s e , c a n c o n s id e r in c r e m e n t c a p a c ito r s .
b7 M S B _ S IG N S in g le _ P W M LVDF DAC
b0 PW MCC PW MC R e g is te r P W M E n a b le 1 : e n a b le 0 : d is a b le D A C e n a b le 1 : e n a b le 0 : d is a b le L V D d e te c tio n fla g 1 : L V D d e te c tio n 0 : L V D n o n - d e te c tio n S in g le P W M O u tp u t 1 : s in g le o u tp u t 0 : d u a l o u tp u ts N o t im p le m e n te d , r e a d a s " 0 " P 1 1 P a r a lle l D a ta P o la r ity 1 : P 1 1 n o n - in v e r t 0 : P 1 1 in v e r t
Pulse Width Modulator Control Register
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Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. No. I/O Options 1 2 3 PA0~PA7: wake-up enable or disable PA0~PA7: pull-high enable or disable PB0~PB3: pull-high enable or disable Options
Oscillator Options 4 OSC type selection: RC or crystal
Watchdog Options 5 6 WDT: enable or disable WDT clock source: WDROSC or T1
PB I/O Port Output Voltage Options 7 VDD_PBIO/VDD type selection: VDD_PBIO or VDD for Port B, SPI, I2C I/O per bit
LVD Options 8 LVD function: enable or disable
SIM Options 9 10 11
2
SIM Function: enable or disable SPI S/W CSEN: enable or disable SPI S/W WCOL: enable or disable
I C Options 12 13 I2C RNIC: enable or disable I2C debounce time: 0/1/2 system clocks
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Application Circuits
VDD=2.7V~3.6V
V
DD
10W 0 .1 m F 47mF
V D D _ P B IO
VDDA
VDDP
VDDF OSC2 OSC1 150kW ~ 300kW
T r a n s is to r O u tp u t V
DD
V
DD
0 .1 m F
SPK (8 W /1 6 W ) 8050 R2
VDD 100mF 100kW RES 0 .1 m F PA0~PA7 PB0~PB3 AUD VS VSS VSS VSS A P F CLK DO DI SCS H T 8 3 F 1 0 /2 0 /4 0 /6 0 /8 0 SCK SI SO CS S
AUD
R1 N o te : R 1 > R 2
P o w e r A m p lifie r O u tp u t
CE 5 AUD 0 .1 m F 2 3 10mF A u d io In 1 OUTN VDD 8
SPK (8 W /1 6 W )
V
DD
H T82V733 VREF NC
47mF 4
6
OUTP 7
V
DD
47mF V D D _ P B IO VDDA VDDP VDDF OSC2 OSC1 V
DD
4M H z~ 8M H z
VDD 100mF 100kW RES 0 .1 m F
PA0~PA7 PB0~PB3 VS VSS VSS VSS A P F SPK (8 W /1 6 W ) S
PW M1 PW M2 CLK DO DI SCS H T 8 3 F 1 0 /2 0 /4 0 /6 0 /8 0 SCK SI SO CS
N o te : T h e P W M
a p p lic a tio n r e fe r to th e d e s c r ip tio n o f P u ls e W id th M o d u la tio n O u tp u t.
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VIN=3.6V~24V
V
DD
10W 0 .1 m F 47mF
V D D _ P B IO
V V
DD
LDO _O UT
IN
L D O _ IN VDD
VDDA
VDDP
VDDF OSC2 OSC1 150kW ~ 300kW PA0~PA7
T r a n s is to r O u tp u t V
DD
0 .1 m F
SPK (8 W /1 6 W ) 8050 R2
AUD PB0~PB3
100mF
R1 N o te : R 1 > R 2
100kW RES
AUD VS VSS VSS VSS A P F S
0 .1 m F
P o w e r A m p lifie r O u tp u t
CE 5 AUD 0 .1 m F 2 3 10mF A u d io In 1 OUTN VDD 8
SPK (8 W /1 6 W )
CLK DO DI SCS
SCK SI SO CS
V
DD
H T82V733 VREF NC
47mF 4
H T 8 3 F 1 0 P /2 0 P /4 0 P /6 0 P /8 0 P
6
OUTP 7
V
DD
47mF V D D _ P B IO VDDA VDDP VDDF OSC2 OSC1 PA0~PA7 PB0~PB3 VS VSS VSS VSS A P F SPK (8 W /1 6 W ) S 4M H z~ 8M H z
V V
DD
LDO _O UT
IN
L D O _ IN VDD
100mF
100kW RES
0 .1 m F PW M1 PW M2 CLK DO DI SCS SCK SI SO CS
H T 8 3 F 1 0 P /2 0 P /4 0 P /6 0 P /8 0 P
N o te : T h e P W M
a p p lic a tio n r e fe r to th e d e s c r ip tio n o f P u ls e W id th M o d u la tio n O u tp u t.
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Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 50 May 12, 2009
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CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
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CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
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RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
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SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
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Package Information
44-pin QFP (10mm10mm) Outline Dimensions
C D G 23 33
H
I 34 22 L F A B E 44 12 K 1 11 a J
Symbol A B C D E F G H I J K L a
Dimensions in mm Min. 13.00 9.90 13.00 9.90 3/4 3/4 1.90 3/4 0.25 0.73 0.10 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.80 0.30 3/4 3/4 3/4 3/4 3/4 0.10 3/4 Max. 13.40 10.10 13.40 10.10 3/4 3/4 2.20 2.70 0.50 0.93 0.20 3/4 7
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, Gaoxin M 2nd, Middle Zone Of High-Tech Industrial Park, ShenZhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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